A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates continuous time linear equalizer, variable gain amplifier, phase interpolator-based clock and data recovery, 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed employed the DFE. The DCMLC, which adopts logic, breaks trade-off between bandwidth to Q delay traditional (CMLC). Compared with CMLC, DCMLC reduces by 36%, allows implementation of Moreover, first tap signals are directly tapped from output allowing current initiate 0.5UI before clock. PAM-4 prototype fabricated 65nm CMOS process. At rate 56-Gbps, it can compensate up 20.17dB achieve bit error $< 1\text{E}$ -10 power efficiency 4.75 pJ/bit.